SASIMI2003 Final Program

Click the paper title to view its (extended) abstract.

April 3, Thursday, 2003

9:15-9:30 Opening

9:30-10:45 Keynote Speech:

"Designing Nano-scale Systems for the Ambient Intelligence World"
Speaker: Hugo J. De Man (Katholieke Univ. Leuven/IMEC, Belgium)
Chair: Shuji Tsukiyama (Chuo Univ., Japan)
While process technologists are obsessed to pursue Moore's curve down to nanoscale dimensions, design technologists are confronted with gigascale complexity. On the other hand, future Ambient Intelligence products require zero cost, zero energy yet software programmable novel system architectures to be sold in huge volumes and be designed in exponentially decreasing time. How do we cope with these novel silicon architectures? What challenges in research does this create? How to create the necessary tools and skills and how to organise research and education in a world driven by shareholders value? This is the subject of this contribution.
10:45-11:00 Break

11:00-11:45 Invited talk 1:

"The Future of IC Design: A Design Technology Point of View"
Speaker: Raul Camposano (Synopsys, USA)
Chair: Masahiro Fujita (Univ. of Tokyo, Japan)
The design of Integrated Circuits is undergoing profound changes. As economic realities shift, geometries shrink, and designers move to higher levels of abstraction, predictable challenges emerge. This presentation explores the main areas that are sure to change the industry and IC design in the near future:
   * Business disruptions, Mask and NRE cost, FPGAs, platform-based design
   * Moore's Law, Complexity and Heterogeneity
   * Manufacturing physics: Signal integrity, Power, Design for Manufacturability
   * Business disruptions, Mask and NRE cost, FPGAs, platform-based
  This presentation will examine these areas from a design technology point of view, focusing on the changes we expect in design and verification.
11:45-13:15 Lunch Break

13:15-14:00 Invited talk 2:

"Advanced Design for Analog-RF and Digital Mixed LSIs --Crosstalk Noise Evaluation and Reduction--"
Speaker: Atsushi Iwata (Hiroshima Univ., Japan)
Chair: Hidetoshi Onodera (Kyoto Univ., Japan)

  In the coming multi-giga network and post-digital computer era, high performance analog-RF mixed signal integration becomes a key technology. Design for these LSIs have to solve many problems. Especially substrate crosstalk or coupling noise between digital and analog circuits through a chip substrate is most difficult. To resolve the problem and integrate accurate and wideband analog functions, substrate noise measurement and simulation techniques have been intensively studied. Noise detection techniques utilizing an on-chip latch-comparator and CMOS logic noise sources were developed. A voltage resolution of 100-uV and 100-ps sampling were achieved at 1-GHz bandwidth using a mixed signal VLSI testing environment. For pre and post P\&R noise simulations on a chip level, models for noise injection to and transmission through a substrate, and a noise generation model of CMOS logic gates were developed. Simulation results are well reproduces the measurement result within a 10% error. Design methodology for reducing crosstalk noise is also discussed, which includes a low-noise CMOS logic circuit.
14:00-15:30 Poster Session 1: Logic Level Design/Physical Design I
Chairs: Hiro Tsujikawa (Matsushita Elec. Ind., Japan )
Yutaka Tamiya (Fujitsu Lab., Japan )
"A Logic-Synthesis-Friendly RTL Description Style in the SpecC Language", Y. Sakai(Toshiba Corp., Japan), M. Fujita(Univ. of Tokyo, Japan)
"A Design-for-Verification Technique for Reducing Debugging Efforts in HDL", C. J. Liu(National Central Univ., Taiwan)
"Assertion Monitor Based Verification Methodology for Hardware Verification", S. M. B, M. P, A. S. T. B(International Inst. of Information Technology,Hyderabad, India), K. K. D(Mentor Graphics (India) Ltd, India)
"A Layout Design Approach for Low Power Circuits Using On-the-fly Generation of Pass Transistor Logic Cells Based on BDD Structure", K. Fukuoka, M. Numa, K. Yamamoto(Kobe Univ., Japan), H. Kondoh(Kawasaki Microelectronics, Inc., Japan)
"A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization", G. Fey, R. Drechsler(Univ. of Bremen, Germany)
"An Improved Multiple Error Diagnosis Technique Using Symbolic Simulation with Truth Variables and Its Application to Incremental Synthesis for Standard-Cell Design", H. Inoue, T. Iwasaki, M. Numa, K. Yamamoto(Kobe Univ., Japan)
"Statistical Gate-delay Modeling with Intra-gate Variability", K. Okada, K. Yamaoka, H. Onodera(Kyoto Univ., Japan)
"Extraction of Inter- and Intra-Chip Device-Parameter Variations with a Differential-Amplifier-Stage Test Circuit", T. Mizoguchi, H. J. Mattausch, H. Ueno, D. Kitamaru, K. Hisamitsu, M. Miura-Mattausch(Hiroshima-university, Japan), S. Itoh, K. Morikawa(STARC, Japan)
"Efficient Techniques for Reducing Substrate Model Complexity in Mixed-Signal IC's", H. Lan, Y. Lu(Stanford Univ., USA), N. Nakano(Keio Univ., Japan), R. W. Dutton(Stanford Univ., USA)
"Rectangle-based Layout Conversion for Migration", Y. Choi, I. Chun, B. Kim(Chungnam National Univ., Korea)
"Cell Placement Optimization Using Phase Transition and Annealing by a Metropolis's Monte-Carlo Simulation", M. Toyonaga(Kochi Univ., Japan), K. Kurokawa(Matsushita Elec. Ind. Co.,Ltd., Japan), T. Akino(Kinki Univ., Japan), S. Kuninobu(Kochi Univ., Japan)
"Design Optimization Methodology of On-Chip Spiral Inductor", H. Hoshino, K. Okada, H. Onodera(Kyoto Univ., Japan)
15:30-16:15 Invited talk 3:
"Application-Specific Networks-on-Chips"
Speaker: Wayne Wolf (Princeton Univ., USA)
Chair: Kazutoshi Wakabayashi (NEC, Japan)
Networks-on-chips appear to be a promising technology for system-on-chip design. Not only do they simplify circuit design by partitioning the chip into smaller clock domains, but that same partitioning helps organize the architectural design of the SoC. Because the network is self-contained, we can use CAD techniques to design a custom network-on-chip that is optimized for the requirements of the application. We will survey recent work in networks-on-chips and talk about two problems in particular. First, we will discuss wave pipelining and related circuit techniques for the design of high-performance on-chip network fabrics. Second, we will discuss how network multiprocessors affect the design of embedded systems-on-chips.
16:15-17:45 Poster Session 2: System Level Design/Design Experiences I
Chairs: Yukihiro Iguchi (Meiji Univ., Japan )
Nozomu Togawa (Univ. of Kitakyushu, Japan )
"A Front-end for Better Handling of High-level Hardware Descriptions", L. Gauthier(IST, Japan), N. Devroye, H. Tomiyama, K. Murakami(ISIT, Japan)
"Bit Length Optimization of Fractional Parts on Floating to Fixed Point Conversion for High-Level Synthesis", N. Doi(NAIST, Japan), T. Horiyama(Kyoto Univ., Japan), M. Nakanishi(NAIST, Japan), S. Kimura(Waseda Univ., Japan), K. Watanabe(NAIST, Japan)
"A Voltage Scheduling Technique for Fault-Tolerant Real-Time Microprocessor Systems", T. Ishihara(Univ. of Tokyo, Japan)
"Binding Constrained Scheduling for Iterative Algorithm with Conditional Branches", K. Ohashi, M. Kaneko(JAIST, Japan)
"A Simulator Generator Based on Configurable VLIW Model Considering Synthesizable HW Description and SW Tools Generation", K. Okuda, S. Kobayashi, Y. Takeuchi, M. Imai(Osaka Univ., Japan)
"An Instruction-Set Simulator Generator for SIMD Processor Cores", Y. Miyaoka(Waseda Univ., Japan), N. Togawa(The Univ. of Kitakyushu, Japan), K. Kasahara, J. Choi, M. Yanagisawa, T. Ohtsuki(Waseda Univ., Japan)
"A Prioritized Cache for Multi-tasking Real-Time Systems", Y. Tan, V. J. Mooney III(Georgia Inst. of Tech., USA)
"Hardware Implementation of Binary Morphological Operations Based on Decomposition of Structure Element", K. Thammajong(King Mongkut's Univ. of Tech. Thonburi, other), K. Chamnognthai(The Univ. of the Thai Chamber of Commerce, other), P. Kumhom(King Mongkut's Univ. of Tech. Thonburi, other)
"Architectural Design Space Exploration of Configurable Processors Using ASIP Meister", A. Kitajima(Osaka Electro-Communication Univ., Japan), Y. Takeuchi(Osaka Univ., Japan), A. Shiomi(Shizuoka Univ., Japan), J. Sato(Tsuruoka National College of Tech., Japan), S. Kobayashi, M. Imai(Osaka Univ., Japan)
"Design and Analysis of Hardware Acceleration for Ethernet TCP/IP Checksum Computation", I. Huang, R. Gu, Z. Chen(National Sun Yat-Sen Univ., Taiwan)
"Development of an IP Library of IEEE-754-Standard Single-Precision Floating-Point Dividers", H. Ochi, T. Suzuki, S. Matsunaga, Y. Kawano, T. Tsuda(Hiroshima City Univ., Japan)
"An Associative Memory for Real-Time Applications Requiring Fully Parallel Nearest Manhattan-Distance-Search", T. Koide, Y. Yano, H. J. Mattausch(Hiroshima Univ., Japan)
"A Design of Neural Signal Sensing LSI with Multi-Input-Channels", T. Yoshida, T. Mashimo, M. Akagi, A. Iwata, M. Yoshida, K. Uematsu(Hiroshima Univ., Japan)
18:30-20:30 Banquet (ANA Hotel)

April 4, Friday, 2003

9:00-9:45 Invited talk 4:
"Future of Integrated Circuits Technology for the Internet Era"
Speaker: Yoshio Nishi (Stanford Univ., USA)
Chair: Takashi Kambe (Kinki Univ., Japan)
Integrated circuits technology which has been driven by the Moore's Law and the scaling principle wit h dynamic random access memory initially, followed by high performance microprocessor later as techno logy drivers. The progress made in the past three decades in terms of integration density and cost per function, i.e. cost/bit or cost /gate, has been far exceeding the magnitude of any progresses so far mankind made in our history. The era of PC became possible only with such significant achieveme nts of silicon technology.
  As we see further development of mobile communication/computing or ubiquitous communication and compu ting coming real and growing fast, several new requirements for integrated circuits technology have e volved such as ultra-low power CMOS, analog/RF integration on digital platform, power management and even an on-chip power source. This may be further expanded in order to make break through improveme nt for communication band width from back plane to chip and ultimately on-chip interconnects with pho tonic capability.
  This talk will broadly discuss what have been done in the past decades, and where we are as well as w here we would most likely be heading toward in terms of device technology and interconnect for the in ternet era. Also discussed will be possible impacts from nanotechnology research from which integra ted circuits technology will gain more.
9:45-11:15 Poster Session 3: Logic Level Design/Physical Design II
Chairs: Masanori Hashimoto (Kyoto Univ., Japan )
Yasuhiro Takashima (JAIST, Japan )
"An Approach for Circuit Size Reduction by Variable Reordering for PCA-Chip2", T. Yuasa, A. Tomita, T. Izumi(Kyoto, Japan), T. Onoye(Osaka, Japan), Y. Nakamura(Kyoto, Japan)
"A Method to Realize Logic Functions Using LUTs and OR Gates", M. Matsuura, T. Sasao(Kyushu Inst. of Tech., Japan)
"Dynamic Effective Precision Matching Computation", V. Goulart, K. Murakami(Kyushu Univ., Japan)
"VHDL Modeling of MPEG Audio Decoder", M. B. I. Reaz, M. S. Sulaiman(Multimedia Univ., Malaysia), M. A. M. Ali(Univ. Kebangsaan Malaysia, Malaysia)
"On Strong Locality Properties of Alternative Wires in Digital Circuits", Y. L. Wu(The Chinese Univ. of Hong Kong, Hong Kong), H. Fan(Univ. of Victoria, Canada), W. Wong, K. C. Cheng, C. C. Cheung(The Chinese Univ. of Hong Kong, Hong Kong)
"The Design of Sfl2vl: SFL to Verilog Convertor Based on a LR-parser", N. Shimizu(Tokai Univ., Japan)
"Code Generation for Embedded Systems Using Heterogeneous MDDs", S. Nagayama, T. Sasao(Kyushu Inst. of Tech., Japan)
"Driving Capability by Lateral BJT-CMOS Inverter", T. Akino(Kinki Univ., Japan)
"Timing-Driven Standard Cell Placement with a New Cluster Placement Model", H. Kubota, N. Iwauchi, S. Wakabayashi(Hiroshima Univ., Japan)
"Slew Calculation against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis", Y. Yamada, M. Hashimoto, H. Onodera(Kyoto Univ., Japan)
"Frequency Determination for Interconnect RLC Extraction", A. Tsuchiya, M. Hashimoto, H. Onodera(Kyoto Univ., Japan)
"A Parasitic Capacitance Modeling Method for Non-Planar Interconnects", S. Tani, Y. Uchida, M. Furuie(Osaka Univ., Japan), S. Tsukiyama(Chuo Univ., Japan), B. Lee, S. Nishi, Y. Kubota(SHARP Corp., Japan), I. Shirakawa(Osaka Univ., Japan), S. Imai(SHARP Corp., Japan)
11:15-12:00 Invited talk 5:
"Wire Planning for Timing Closure"
Speaker: Ralph Otten (Technical Univ. Eindhoven, Netherlands)
Chair: Youn-Long Lin (Tsing Hua University, Taiwan)
This paper presents an extension on the recent constant delay methodology in chip design. It is argued that this methodology has a fundamental flaw when wire resistance cannot be neglected. The extension is base on wire planning, an approach where input-output paths are planned before modules are specified, synthesized and sized. If these wires are optimally segmented their delay is linear in the path length and independent of the position of the modules along these paths. From timing requirements the total budget left to modules after allocating the appropriate delay to the wires can be determined. This paper describes how this budget can be divided over the modules. A problem formulation avoiding the size explosion of path-based approaches is introduced and efficient solution is enabled when area-delay trade-offs are convex, a reasonable approximation is practice. Whereas a straight-forward formulation did not allow solving problems of even less than 50 nodes, the proposed approach solved all available benchmarks, the largest with 2000 nodes and close to 10^20 paths, on the same computation hardware.
12:00-13:30 Lunch Break

13:30-14:15 Invited talk 6:

"The MARCO Focus Research Center for Circuits Systems and Software (C2S2): Life at the End of Technology Scaling"
Speaker: Rob A. Rutenbar (Carnegie Mellon Univ., USA)
Chair: Tetsuya Fujimoto (STARC, Japan)

  Moore's law has held true for two decades: every year, transistors get faster, smaller, cheaper. What happens when this scaling stops? We are approaching ultimate physical limits for CMOS devices; we can't make silicon atoms any thinner. As we approach some of these limits, things start to become unpleasant. At 100nm, devices already have unfriendly characteristics--leakage, manufacturing variation, noise, etc. What happens if, at 10nm, these behaviors move from "unfriendly" to "hostile"? What happens if we can no longer assume that most of the devices on a chip work most of the time? I'm going to argue that what has to happen is a whole-scale reinvention of the basic circuit design techniques that we rely on to convert transistors into useful performance, and to hide difficult physics from designers of systems and software who don't want to know about transistors. In 1999, the U.S. semiconductor industry and U.S Department of Defense came together to jointly fund a set of national, multi-university U.S. research centers to tackle these sorts of long range problems. I will describe the research agenda of the center I direct -- C2S2 -- its focus on reinventing a new generation of circuit solution strategies, and how these might enable us to continue to convert transistors into useful performance.
14:15-15:45 Poster Session 4: System Level Design/Design Experiences II
Chairs: Tomonori Izumi (Kyoto Univ., Japan )
Hiroshi Date (System JD, Japan )
"Verification Environment for C-Based Design", H. Makida, T. Morishita, M. Ohnishi, K. Okada, A. Yamada, T. Kambe(Sharp Corp., Japan), P. Boca(Sharp Laboratories of Europe Limited, UK)
"Optimized Bank-Based Multi-Port Memories through a Hierarchical Multi-Bank Structure", S. Fukae, N. Omori, H. J. Mattausch, T. Koide(Hiroshima Univ., Japan), T. Inoue, T. Hironaka(Hiroshima City Univ., Japan)
"Behavioral Simulation Techniques for Substrate Noise Analysis in PLL Circuits", J. W. Kim(Stanford Univ., USA), M. H. Perrott(M.I.T., USA), R. W. Dutton(Stanford Univ., USA)
"High-level Control Flow Transformations for Performance Improvement of Address-Dominated Multimedia Applications", H. Falk(Univ. of Dortmund, Germany), C. Ghez, M. Miranda(IMEC Lab., Belgium), R. Leupers(RWTH Aachen Univ., Germany)
"An Efficient Power and Performance Evaluation Method with Reconfigurable Bus Architecture Model", M. Takahashi, H. Miyajima, M. Fukui(Matsushita, Japan)
"Heterogeneous Processor Architecture and Its Design Methodology to Shorten the Design Period of Embedded SoCs", Y. Yuyama, M. Aramoto, K. Takai(Kyoto Univ., Japan), K. Kobayashi(Tokyo Univ., Japan), H. Onodera(Kyoto Univ., Japan)
"DX-Gt: Memory Management and Crossbar Switch Generator for Multiprocessor System-on-a-Chip", M. A. Shalan, E. S. Shin, V. J. Mooney III(Georgia Tech, USA)
"VLSI Architecture for MPEG-4 Core Profile Codec Core", T. Nakagawa, G. Fujita, T. Onoye, I. Shirakawa(Osaka Univ., Japan)
"Scalable Design Framework for JPEG2000 Encoder Architecture", Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, Y. Nakamura(Kyoto Univ., Japan)
"Implementing Image Processing Algorithms on FPGA-based Realtime Vision System", S. Hirai, M. Zakouji, T. Tsuboi(Ritsumeikan Univ., Japan)
"Taking Over Mechanism: a Cooperation Methodology of Hardware and Software in Network Controllers", K. Watanabe, H. Amano(Keio Univ., Japan), J. Yamamoto(Hitachi, Ltd. Central Research Laboratory, Japan), J. Tsuchiya, T. Otsuka(Keio Univ., Japan), T. Kudoh(National Inst. of Advanced Industrial Science and Tech., Japan)
"High Access Bandwidth Multi-Port-Cache Design with Compact Hierarchical 1-Port-Bank Structure", Z. Zhu, K. Johguchi(Hiroshima Univ., Japan), T. Hirakawa(Hiroshima City Univ., Japan), H. J. Mattausch, T. Koide(Hiroshima Univ., Japan), T. Hironaka(Hiroshima City Univ., Japan)
"A Novel Wide Operating Range Technique of Delay-Locked Loop with Frequency Selection Block", W. Chang, C. Lien, T. He(Tamkang Univ., Taiwan)
15:45-17:15 Panel discussion:
"Everything Is (Re-) Programmable and (Re-) Configurable: How Much ``Hardware'' Is Still Needed?"
Organizer:Wolfgang Rosenstiel (Univ. of Tuebingen, Germany)
Panelists:Raul Camposano (Synopsys, USA)
Hugo J. De Man (Katholieke Univ. Leuven/IMEC, Belgium)
Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Rob A. Rutenbar (Carnegie Mellon Univ., USA)
It seems that time to market is the most important optimization goals in today's chip design projects. To reach this goal fully programmable and configurable systems on chip (CSOC) are advertised. Even late engineering and specification changes should be possible after production. Furthermore techniques are developed to even change the functions of chips after production in order to extend the products life cycle without a new production run. Are software programmability and run time hardware reconfigurability really the solutions for implementing complex chips in a short time with less non-recurring engineering costs? Panelists with different opinions will discuss with the audience the pros and cons of these approaches.
17:15-17:30 Closing