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The 14th Workshop on Synthesis And System Integration of Mixed Information technologies

FPGA, Place & Route
Time: 14:10 - 15:50 Monday, October 15, 2007
Location: Conference Hall (2F) & Poster Room (2F)
Chairs: Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Yasuhiro Takashima (Univ. of Kitakyushu, Japan)

R2-1 (Time: 14:10 - 14:12)
TitleA BCH Decode Accelerator for Application Specific Processors
Author*Kazuhito Ito (Saitama Univ., Japan)
Pagepp. 115 - 121
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R2-2 (Time: 14:12 - 14:14)
TitleDesign and FPGA Implementation of a High-Speed String Matching Engine
Author*Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ., Japan)
Pagepp. 122 - 129
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R2-3 (Time: 14:14 - 14:16)
TitleSpeed Improvement of AES Encryption using Hardware Acclererators Synthesized by C Compatible Architecture Prototyper (CCAP)
Author*Hiroyuki Kanbara (ASTEM RI, Japan), Takayuki Nakatani, Naoto Umehara (Ritsumeikan Univ., Japan), Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Hiroyuki Tomiyama (Nagoya Univ., Japan)
Pagepp. 130 - 134
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R2-4 (Time: 14:16 - 14:18)
TitleA Hybrid Logic Simulator Using LUT Cascade Emulators
Author*Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech., Japan)
Pagepp. 135 - 141
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R2-5 (Time: 14:18 - 14:20)
TitleStatistical Estimation Method for Verification Coverage Using FPGA-based Emulators
Author*Kohei Hosokawa, Yuichi Nakamura (NEC, Japan), Baku Haraguchi (NEC Micro Systems, Japan)
Pagepp. 142 - 146
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R2-6 (Time: 14:20 - 14:22)
TitleBlockage-Aware Routing Tree Construction with Concurrent Buffer and Flip-Flop Insertion
AuthorShu-Yun Chen (Realtek Semiconductor Corp., Taiwan), *Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 147 - 154
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R2-7 (Time: 14:22 - 14:24)
TitleLow-Power Clock Tree Synthesis by Low-Swing Techniques
AuthorYun-Ta Lin (SpringSoft, Inc., Taiwan), *Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Pagepp. 155 - 160
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R2-8 (Time: 14:24 - 14:26)
TitlePost-Silicon Clock-timing Tuning Based on Statistical Estimation
Author*Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitakyushu, Japan), Yuichi Nakamura (NEC Corp., Japan)
Pagepp. 161 - 165
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R2-9 (Time: 14:26 - 14:28)
TitleSpeed Enhancement Technique for the Post-fabrication Clock-timing Adjustment of Digital LSIs
Author*Tatsuya Susa (Toho Univ., Japan), Masahiro Murakawa, Eiichi Takahashi (AIST, Japan), Tatsumi Furuya (Toho Univ., Japan), Tetsuya Higuchi (AIST, Japan), Shinji Furuichi, Yoshitaka Ueda, Atsushi Wada (Sanyo Electric Co., Ltd, Japan)
Pagepp. 166 - 173
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R2-10 (Time: 14:28 - 14:30)
TitleRepairs for Voltage Drop and Noise Violation in Late Design Stages
AuthorShih-Tsung Huang (AnaGlobe Technology, Taiwan), *Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Pagepp. 174 - 178
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R2-11 (Time: 14:30 - 14:32)
TitleEstimation of Yield Enhancement by Critical Path Reconfiguration Utilizing Random Variations on Deep-submicron FPGAs
Author*Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 179 - 183
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R2-12 (Time: 14:32 - 14:34)
TitleA Mixed Integer Linear Programming Based Approach for Post-Routing Redundant Via Insertion
AuthorKuang-Yao Lee, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Kai-Yuan Chao (Intel Corp., United States)
Pagepp. 184 - 191
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R2-13 (Time: 14:34 - 14:36)
TitleFast Monotonic Via Assignment Excluding Mold Gates for 2-Layer Ball Grid Array Packages
Author*Yoichi Tomioka, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Pagepp. 192 - 197
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R2-14 (Time: 14:36 - 14:38)
TitleAn I/O Planning Method for Three-Dimensional Integrated Circuits
Author*Chao-Hung Lu (National Central Univ., Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Chien-Nan Jimmy Liu, Wen-Yu Shih (National Central Univ., Taiwan)
Pagepp. 198 - 202
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R2-15 (Time: 14:38 - 14:40)
TitleNon-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment
Author*Wen-Nai Cheng, Yu-Ning Chang, Yih-Lang Li (National Chiao-Tung Univ., Taiwan)
Pagepp. 203 - 207
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R2-16 (Time: 14:40 - 14:42)
TitleFujimaki-Takahashi Squeeze : Linear Time Construction of Constraint Graphs of a Floorplan for a Given Permutation
Author*Ryo Fujimaki, Toshihiko Takahashi (Niigata Univ., Japan)
Pagepp. 208 - 213
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R2-17 (Time: 14:42 - 14:44)
TitlePlacement with Symmetry Constraints for Analog IC Layout Design based on Tree Representation
Author*Natsumi Hirakawa, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Pagepp. 214 - 221
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