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The 14th Workshop on Synthesis And System Integration of Mixed Information technologies

System Level Design & Logic Synthesis
Time: 9:45 - 11:30 Tuesday, October 16, 2007
Location: Conference Hall (2F) & Poster Room (2F)
Chairs: Bernard Courtois (CMP, France), Yukio Mitsuyama (Osaka Univ., Japan)

R4-1 (Time: 9:45 - 9:47)
TitleAn Object-Oriented Circuit Design Method and Its Evaluation
Author*Seigo Masuoka, Hiroyuki Terai, Manabu Koyama (Kinki Univ., Japan), Kazuhiko Nakahara (Spansion Japan Corp., Japan), Akihisa Yamada (Sharp Corp., Japan), Takashi Kambe (Kinki Univ., Japan)
Pagepp. 337 - 342
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R4-2 (Time: 9:47 - 9:49)
TitleObject Oriented Design and Synthesis of Communication in Hardware-/Software Systems with OSSS
Author*Kim Grüttner, Cornelia Grabbe, Frank Oppenheimer (OFFIS - Institute for Information Technology, Germany), Wolfgang Nebel (Carl v. Ossietzky Univ. Oldenburg, Germany)
Pagepp. 343 - 350
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R4-3 (Time: 9:49 - 9:51)
TitleA Data Arrangement Method for Block Floating Point Systems
Author*Takashi Hamabe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Pagepp. 351 - 356
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R4-4 (Time: 9:51 - 9:53)
TitleCalling Software Functions from Hardware Functions in High-Level Synthesizer CCAP
Author*Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori (Kwansei Gakuin Univ., Japan), Hiroyuki Kanbara (ASTEM RI, Japan), Hiroyuki Tomiyama (Nagoya Univ., Japan)
Pagepp. 357 - 360
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R4-5 (Time: 9:53 - 9:55)
TitlePerformance-Aware Communication Architecture Synthesis
Author*Alexander Viehl, Oliver Bringmann (FZI Forschungszentrum Informatik, Germany), Wolfgang Rosenstiel (Univ. Tübingen, Germany)
Pagepp. 361 - 368
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R4-6 (Time: 9:55 - 9:57)
TitleA Network Processor Synthesis System for Task-Chaining Network Applications
Author*Youhua Shi, Keishi Nakayama, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan)
Pagepp. 369 - 374
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R4-7 (Time: 9:57 - 9:59)
TitleResynthesis Method for Circuit Acceleration on LUT-based FPGA
Author*Weijie Xing (Waseda Univ., Japan), Takashi Horiyama (Saitama Univ., Japan), Shunichi Kuromaru, Tomoo Kimura (Matsushita Electric Industrial Co., Ltd, Japan), Shinji Kimura (Waseda Univ., Japan)
Pagepp. 375 - 380
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R4-8 (Time: 9:59 - 10:01)
TitleSAT Based Boolean Matching for Incompletely Specified Functions
Author*Kuo-Hua Wang, Chung-Ming Chan (Fu Jen Catholic Univ., Taiwan)
Pagepp. 381 - 388
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R4-9 (Time: 10:01 - 10:03)
TitleAn Error Diagnosis Technique Based on Specifications with Don't Cares
Author*Narumi Okada, Takayuki Iida, Toshiro Ishihara, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 389 - 396
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R4-10 (Time: 10:03 - 10:05)
TitleAn LUT-Based Error Diagnosis Technique Extended for Multiple Missing Line Errors Based on Iterative Diagnosis Procedure
Author*Toshiro Ishihara, Ryosuke Arai, Narumi Okada, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 397 - 404
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R4-11 (Time: 10:05 - 10:07)
TitleMixed-Abstraction Level Co-Simulation Environment for Dynamically Reconfigurable Processor Arrays
Author*Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ., Japan)
Pagepp. 405 - 411
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R4-12 (Time: 10:07 - 10:09)
TitleBlack-Diamond: a Retargetable Compiler using Graph with Configuration Bits for Dynamically Reconfigurable Architectures
Author*Vasutan Tunbunheng, Hideharu Amano (Keio Univ., Japan)
Pagepp. 412 - 419
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R4-13 (Time: 10:09 - 10:11)
TitleA Reconfigurable Architecture with Special Functions for Shift Keying
Author*Ayataka Kobayashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan)
Pagepp. 420 - 426
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R4-14 (Time: 10:11 - 10:13)
TitleTopology Generation and Floorplanning for Low Power Application-Specific Network-on-Chips
Author*Wan-Yu Lee, Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan)
Pagepp. 427 - 432
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R4-15 (Time: 10:13 - 10:15)
TitleFloorplan-Aware Design Methodology for Application-Specific Bus Matrix Systems
Author*Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou (National Chiao Tung Univ., Taiwan)
Pagepp. 433 - 438
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R4-16 (Time: 10:15 - 10:17)
TitleLow Power Object Oriented Synthesis for Electronic System-Level Design
Author*Mehdi Kamal, Shaahin Hessabi (Sharif Univ. of Tech., Iran)
Pagepp. 439 - 444
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