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The 15th Workshop on Synthesis And System Integration of Mixed Information technologies

Poster III: High Performance and Special Feature Design
Time: 16:45 - 18:30 Monday, March 9, 2009
Location: Manza & Kaneohe
Chairs: Nobuyuki Nishiguchi (STARC, Japan), Hiroyuki Higuchi (Fujitsu Microelectronics Ltd., Japan)

R3-1 (Time: 16:45 - 16:48)
TitleEvaluation of the Performance of the MIMD Mode of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application
Author*Shohei Nomoto, Shorin Kyo, Shinichiro Okazaki (NEC, Japan)
Pagepp. 201 - 206
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R3-2 (Time: 16:48 - 16:51)
TitlePipelining SHA-2 Implementations using Carry Save Adders
Author*Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi (Ritsumeikan Univ., Japan)
Pagepp. 207 - 212
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R3-3 (Time: 16:51 - 16:54)
TitleHardware Accelerator for Feature Point Detection Part of SIFT Algorithm & Corresponding Hardware-Friendly Modification
Author*Jingbang Qiu, Tianci Huang, Takeshi Ikenaga (Waseda Univ., Japan)
Pagepp. 213 - 218
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R3-4 (Time: 16:54 - 16:57)
TitleVariability Characterization and Tolerance on Throughput and Power for Chip-Multiprocessors
Author*Wan-Yu Lee, Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan)
Pagepp. 219 - 223
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R3-5 (Time: 16:57 - 17:00)
TitleA Ternary Multi-Ported Content Addressable Memory Architecture utilizing Asynchronous Multiple Search-Operation Technology
Author*Takeshi Kumaki, Masaharu Tagami, Yuta Imai, Tetsushi Koide, Hans Jürgen Mattausch (Hiroshima Univ., Japan)
Pagepp. 224 - 229
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R3-6 (Time: 17:00 - 17:03)
TitleA Hardware Design for the First Pass of A Large Vocabulary Continuous Speech Recognition System
Author*Akihiko Eguchi, Joe Hashimoto (Kinki Univ., Japan), Makoto Saituji (NEC Electronics, Japan), Akihisa Yamada (Sharp Corp., Japan), Takashi Kambe (Kinki Univ., Japan)
Pagepp. 230 - 235
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R3-7 (Time: 17:03 - 17:06)
TitleCoarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability
Author*Younghun Ko, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan)
Pagepp. 236 - 241
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R3-8 (Time: 17:06 - 17:09)
TitleLow Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm
Author*Ming-Chih Chen (National Kaohsiung First Univ. of Science and Tech., Taiwan), Shen-Fu Hsiao (National Sun Yat-Sen Univ., Taiwan)
Pagepp. 242 - 247
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R3-9 (Time: 17:09 - 17:12)
TitleDSP Array Breadboard System for Application on Foreground Segmentation
Author*Bin Wu, Takao Nishitani (Tokyo Metropolitan Univ., Japan)
Pagepp. 248 - 253
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R3-10 (Time: 17:12 - 17:15)
TitleAn Interface for Representing Dynamically Reconfigurable Architectures by using Graph with Configuration Information
Author*Vasutan Tunbunheng, Hideharu Amano (Keio Univ., Japan)
Pagepp. 254 - 259
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R3-11 (Time: 17:15 - 17:18)
TitleA Case Study of Clockless Bundled-data On-chip Interconnect Design using Double Edge Triggered Flip-flops
Author*Katsunori Tanaka, Yuichi Nakamura (NEC Corp., Japan)
Pagepp. 260 - 265
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R3-12 (Time: 17:18 - 17:21)
TitleA VLSI Architecture of Tone Classification Function-Based Isolated-Word Speech Recognition
Author*Jirabhorn Chaiwongsai, Werapon Chiracharit, Kosin Chamnongthai (King Mongkut's Univ. of Tech. Thonburi, Thailand), Yoshikazu Miyanaga (Hokkaido Univ., Japan), Kouji Higuchi (Univ. of Electro-Communications, Japan)
Pagepp. 266 - 270
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R3-13 (Time: 17:21 - 17:24)
TitleSpeculative Configuration Prefetching for Multi-Context Architectures
Author*Sven Eisenhardt, Julio Oliveira, Tommy Kuhn, Wolfgang Rosenstiel (Univ. Tübingen, Germany)
Pagepp. 271 - 276
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R3-14 (Time: 17:24 - 17:27)
TitleEfficient Mode Selection Algorithm for Inter-Layer Residual Prediction of H.264/SVC
Author*Yoshitaka Morigami, Shinpei Matsuoka, Tian Song, Takashi Shimamoto (Tokushima Univ., Japan)
Pagepp. 277 - 282
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R3-15 (Time: 17:27 - 17:30)
TitleA Case Study on AES Encryption System Design with SystemBuilder
Author*Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ., Japan)
Pagepp. 283 - 288
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