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The 15th Workshop on Synthesis And System Integration of Mixed Information technologies

Poster IV: Physical Design and Methodology
Time: 9:45 - 11:30 Tuesday, March 10, 2009
Location: Manza & Kaneohe
Chairs: Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Yasuhiro Takashima (Univ. of Kitakyushu, Japan)

R4-1 (Time: 9:45 - 9:48)
TitleA Two-Layer Global Router for Ball Grid Array Packages
AuthorYung-Chia Lin, *Kuang-Yao Lee, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 301 - 306
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R4-2 (Time: 9:48 - 9:51)
TitleA Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages
Author*Yoshiaki Kurata, Yoichi Tomioka, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Pagepp. 307 - 312
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R4-3 (Time: 9:51 - 9:54)
TitleThroughput-Driven Hierarchical Partitioning-Based Placement for Regular Distributed Register Architecture
Author*Ya-Shih Huang, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Pagepp. 313 - 317
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R4-4 (Time: 9:54 - 9:57)
TitleOverlap-aware Analytical Placement Based on Stable-LSE
Author*Naoto Funatsu, Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Pagepp. 318 - 323
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R4-5 (Time: 9:57 - 10:00)
TitleYield Improvement in Gridless Detailed Routing with Redundant Via Insertion
Author*Chih-Ta Lin, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Pagepp. 324 - 329
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R4-6 (Time: 10:00 - 10:03)
TitleInterconnect Utilization of the VPEX Via-Programmable Structured ASIC
Author*Kazuma Kitamura, Syouta Yamada, Masahide Kawarasaki, Yuuichi Kokusyou (Ritsumeikan Univ., Japan), Usman Ahmed, Guy Lemieux (Univ. of British Columbia, Canada), Masaya Yoshikawa (Meijo Univ., Japan), Takeshi Fujino (Ritsumeikan Univ., Japan)
Pagepp. 330 - 334
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R4-7 (Time: 10:03 - 10:06)
TitleSlack-Driven Obstacle-Avoiding Rectilinear Steiner Tree Routing
Author*Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Pagepp. 335 - 340
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R4-8 (Time: 10:06 - 10:09)
TitleFLEC: A Framework for System-level Debugging Support, Formal Verification and Static Analysis
Author*Yoshihisa Kojima, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo, Japan)
Pagepp. 341 - 346
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R4-9 (Time: 10:09 - 10:12)
TitleLanguage-Controlled Integrated Debugging Technique
Author*Noriaki Suzuki, Junji Sakai (NEC Corp., Japan)
Pagepp. 347 - 351
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R4-10 (Time: 10:12 - 10:15)
TitleSoft-error Resiliency Evaluation on Delayed Multiple-modular Flip-Flops
Author*Jun Furuta, Yusuke Moritani, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 352 - 357
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R4-11 (Time: 10:15 - 10:18)
TitleEvaluation of Statistical Method of Estimating Coverage Metrics for Functional Verification
AuthorKohei Hosokawa, *Yuichi Nakamura (NEC, Japan)
Pagepp. 358 - 363
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R4-12 (Time: 10:18 - 10:21)
TitleA Fast Approximation Method of Maximum Operation in Statistical Static Timing Analysis for Achieving Specified Yield
Author*Shun Gokita, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Pagepp. 364 - 369
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R4-13 (Time: 10:21 - 10:24)
TitleDynamic Model of a Parallel Plate Actuator with Pull-in Consideration for CMOS-MEMS Simultaneous Behavior Anticipation
Author*Yuheon Yi, Hiroyuki Fujita, Hiroshi Toshiyoshi (Univ. of Tokyo, Japan)
Pagepp. 370 - 373
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R4-14 (Time: 10:24 - 10:27)
TitleSupport System for ASIC Design based on Sysem Block Diagram
Author*Koichi Mori (Tokyo Metropolitan Univ., Japan), Yuichi Nakamura (NEC, Japan), Takao Nishitani (Tokyo Metropolitan Univ., Japan)
Pagepp. 374 - 379
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R4-15 (Time: 10:27 - 10:30)
TitleEquivalence Checking of Loops Before and After Pipelining by Applying Symbolic Simulation and Induction
Author*Shanghua Gao, Takeshi Matsumoto, Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo, Japan)
Pagepp. 380 - 385
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