| Abstract | Variability due to manufacturing, environmental and aging
uncertainties constitutes one of the major challenges in continuing
CMOS scaling. Worst-case design is simply not feasible any more. This
presentation will describe how statistical timing techniques can be
used to reduce pessimism, achieve full-chip and full-process coverage,
and enable robust design practices. A practical ASIC timing
methodology based on statistical timing will be described.
Model-to-hardware correlation, at-speed test and robust optimization
techniques will be presented. Key research initiatives that were
required to achieve such a design flow will be described. |