Title | Replacement of Flip-Flops by Latches and Pulsed Latches for Power and Timing Optimization |
Author | Yao-Ting Wu, *Rung-Bin Lin (Yuan Ze Univ., Taiwan) |
Page | pp. 300 - 304 |
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Title | A Routability-oriented Packing Method for FPGA with Fracturable Logic Elements |
Author | Wei Chen (Waseda Univ., Japan), Yuichi Nakamura (NEC Corp., Japan), *Nan Liu, Takeshi Yoshimura (Waseda Univ., Japan) |
Page | pp. 305 - 310 |
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Title | A Two-Step BIST Scheme for Operational Amplifier |
Author | *Jun Yuan, Masayoshi Tachibana (Kochi Univ. of Tech., Japan) |
Page | pp. 311 - 316 |
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Title | Circuit Partitioning Methods for FPGA-based ASIC Emulator using High-speed Serial Wires |
Author | *Katsunori Takahashi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ., Japan) |
Page | pp. 317 - 318 |
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Title | Timing-aware Description Methods and Gate-level Simulation of Single Flux Quantum Logic Circuits |
Author | *Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan) |
Page | pp. 319 - 324 |
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Title | Design and Analysis of Via-Configurable Routing Fabrics for Structured ASICs |
Author | Hsin-Pei Tsai, *Rung-Bin Lin, Liang-Chi Lai (Yuan Ze Univ., Taiwan) |
Page | pp. 325 - 329 |
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Title | Device-level Simulations of Parasitic Bipolar Mechanisim on Preventing MCUs of Redundant Filp-Flops |
Author | *Kuiyuan Zhang, Ryosuke Yamamoto, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan) |
Page | pp. 330 - 333 |
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Title | A Method of Analog IC Placement with Common Centroid Constraints |
Author | *Keitaro Ue, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan) |
Page | pp. 334 - 339 |
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Title | GPU-based Line Probing Techniques for Mikami Routing Algorithm |
Author | *Chiu-Yi Chan (Yuan Ze Univ., Taiwan), Jiun-Li Lin (National Cheng Kung Univ., Taiwan), Lung-Sheng Chien (National Tsing Hua Univ., Taiwan), Tsung-Yi Ho (National Cheng Kung Univ., Taiwan), Yi-Yu Liu (Yuan Ze Univ., Taiwan) |
Page | pp. 340 - 344 |
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Title | Topology Design for Power Delivery in 3-D Integrated Circuits |
Author | *Shu-Han Wei, Yi-Hsuan Lee, Chih-Ting Sun, Yu-Min Lee (National Chiao Tung Univ., Taiwan), Liang-Chia Cheng (ITRI, Taiwan) |
Page | pp. 345 - 350 |
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Title | A Spur-Reduction Frequency Synthesizer For Wireless Application |
Author | *Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung (National Chiao Tung Univ., Taiwan) |
Page | pp. 351 - 354 |
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Title | Definite Feature of Low-Energy Operation of Scaled Cross-Current Tetrode (XCT) SOI CMOS Circuits |
Author | *Yasuhisa Omura, Daishi Ino (Kansai Univ., Japan) |
Page | pp. 355 - 360 |
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Title | A Matching Method for Look-ahead Assertion on Pattern Independent Regular Expression Matching Engine |
Author | *Yoichi Wakaba, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ., Japan) |
Page | pp. 361 - 366 |
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Title | Highly-parallel AES Processing for Five Confidentiality Modes with Massive-Parallel SIMD Matrix Processor |
Author | *Hiroki Yoshikawa, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ., Japan) |
Page | pp. 367 - 371 |
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Title | A Trace-Back Method with Source States and its Application to Viterbi Decoders of Low Power and Short Latency |
Author | *Kazuhito Ito (Saitama Univ., Japan) |
Page | pp. 372 - 377 |
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Title | Evaluation of Migration Methods for Island Based Parallel Genetic Algorithm on CUDA |
Author | *Yuri Ardila, Shigeru Yamashita (Ritsumeikan Univ., Japan) |
Page | pp. 378 - 383 |
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Title | FPGA Design of User Monitoring System for Display Power Control |
Author | *Tomoaki Ando, Vasily Moshnyaga (Fukuoka Univ., Japan) |
Page | pp. 384 - 389 |
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Title | A Debug Solution with Synchronizer for CDC |
Author | *Akitoshi Matsuda (Kyushu Univ., Japan), Shinichi Baba (Kyushu Embedded Forum, Japan) |
Page | pp. 390 - 393 |
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Title | A Low Power-Delay Product Processor Using Multi-valued Decision Diagram Machine |
Author | *Hiroki Nakahara (Kagoshima Univ., Japan), Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech., Japan) |
Page | pp. 394 - 395 |
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Title | A TMR-based Soft Error Mitigation Technique With Less Area Overhead in High-Level Synthesis |
Author | Daiki Tsuruta, *Masayuki Wakizaka, Yuko Hara-Azumi, Shigeru Yamashita (Ritsumeikan Univ., Japan) |
Page | pp. 396 - 401 |
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Title | Pipeline Circuit Synthesis from C Descriptions for Fast Memory Access in System LSI |
Author | *Yu-ichi Kitamura (Kinki Univ., Japan), Kazuya Kishida (Panasonic Industrial Devices S&T, Japan), Takashi Kambe (Kinki Univ., Japan) |
Page | pp. 402 - 407 |
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Title | A PE-based Pipelining and Assignment Algorithm for Coarse Grained Dynamic Reconfigurable Circuits |
Author | *Nobuyuki Araki, Takashi Kambe (Kinki Univ., Japan) |
Page | pp. 408 - 413 |
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Title | High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement |
Author | *Yuko Hara-Azumi (Univ. of California, Irvine, U.S.A.), Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeikan Univ., Japan), Nikil D. Dutt (Univ. of California, Irvine, U.S.A.) |
Page | pp. 414 - 419 |
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Title | A Method of Power Supply Voltage Assignment and Scheduling of Operations to Reduce Energy Consumption of Error Detectable Computations |
Author | *Yuki Suda, Kazuhito Ito (Saitama Univ., Japan) |
Page | pp. 420 - 424 |
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Title | Software Design Methodology based on Energy Consumption Model Considering Relationship between Software and Hardware |
Author | *Koji Kurihara, Hiromasa Yamauchi, Toshiya Otomo, Takahisa Suzuki (Fujitsu Laboratories Ltd., Japan), Yuta Teranishi (Fujitsu Kyushu Network Technologies Ltd., Japan), Koichiro Yamashita (Fujitsu Laboratories Ltd., Japan) |
Page | pp. 425 - 430 |
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Title | Electro-Thermal Modeling and Reliability Simulation of Power MOSFETs with SystemC-AMS - Case Study: An Unclamped Inductive Switching Test Circuit |
Author | *Keiji Nakabayashi, Takahiro Ozasa (Keirex Technology Inc., Japan), Tamiyo Nakabayashi (Nara Women's Univ., Japan) |
Page | pp. 431 - 436 |
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