Title | Design Automation for Digital Microfluidic Biochips: From Fluidic-Level Toward Chip-Level |
Author | Tsung-Wei Huang, *Tsung-Yi Ho (National Cheng Kung Univ., Taiwan) |
Page | pp. 439 - 444 |
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Title | Timing-Aware Clock Gating Algorithm for Pulse-Latch Circuits |
Author | *Zong-Han Yang, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan) |
Page | pp. 445 - 450 |
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Title | Resistivity-based Modeling of Substrate Non-uniformity for Resistance Extraction of Low-Resistivity Substrate |
Author | *Yasuhiro Ogasahara, Toshiki Kanamoto (Renesas Electronics Corp., Japan), Hisato Inaba, Toshiharu Chiba (Renesas Design Corp., Japan) |
Page | pp. 451 - 456 |
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Title | Temperature-Constrained Fixed-Outline Floorplanning for 3D ICs |
Author | Ciao-Yu Hong, Wai-Kei Mak, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan) |
Page | pp. 457 - 459 |
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Title | A GPGPU Implementation of Parallel Backward Euler Algorithm for Power Grid Circuit Simulation |
Author | Lei Lin, *Hayato Shiono, Makoto Yokota, Masahiro Fukui (Ritsumeikan Univ., Japan) |
Page | pp. 460 - 465 |
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Title | A Third Order Delta-Sigma Modulator with Shared Opamp Technique for Wireless Applications |
Author | *Ghazal Fahmy, Daisuke Kanemoto, Haruichi Kanaya, Ramesh Pokharel, Keiji Yoshida (Kyushu Univ., Japan) |
Page | pp. 466 - 467 |
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Title | A Self-Organization Maps Approach to FPGA Placement |
Author | Motoki Amagasaki, *Yasuaki Tomonari, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ., Japan) |
Page | pp. 468 - 469 |
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Title | The Development of CAD System for Via Programmable Structured ASIC VPEX3 |
Author | *Ryohei Hori (Ritsumeikan Univ., Japan), Masaya Yoshikawa (Meijo Univ., Japan), Takeshi Fujino (Ritsumeikan Univ., Japan) |
Page | pp. 470 - 475 |
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Title | Design of Low-Voltage High-Precision Complex Quadrature Modulators |
Author | *Takahiro Tsushima, Tsuneo Tsukahara (Univ. of Aizu, Japan) |
Page | pp. 476 - 481 |
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Title | A Design of 2GHz Band O-QPSK Wireless Transmitter using 0.18µmCMOS Technology |
Author | *Yuki Mitani, Nobuhiko Nakano (Keio Univ., Japan) |
Page | pp. 482 - 483 |
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Title | A 0.5V PWM-Driven Analog Differential Amplifier Using Subthreshold Leakage Current |
Author | *Tomochika Harada, Ryuuya Otaki (Yamagata Univ., Japan) |
Page | pp. 484 - 487 |
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Title | 16PE 3D-Mesh NOC Based 3D Multicore Design and Implementation |
Author | Mohamad Hairol Jabbar (ENSTA ParisTech, France), Dominique Houzet (GIPSA-LAB, France), *Omar Hammami (ENSTA ParisTech, France) |
Page | pp. 488 - 489 |
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Title | A Performance Improvement for Floating-Point Arithmetic Unit with Precision Degradation Detection |
Author | *Soseki Aniya, Toshiaki Kitamura (Hiroshima City Univ., Japan) |
Page | pp. 490 - 491 |
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Title | Hardware Architecture for Real-Time Operation of Learning-Based Super-Resolution Using Binary Search Tree |
Author | *Takahiro Kitayama, Kohei Michibata, Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 492 - 496 |
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Title | Architecture Optimization of Group Signature Circuits for Cloud Computing Environment |
Author | *Sumio Morioka, Jun Furukawa, Yuichi Nakamura, Kazue Sako (NEC Corp., Japan) |
Page | pp. 497 - 502 |
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Title | Efficient Packet Transmission Priority Control Method for Network-on-Chip |
Author | *Yusuke Sekihara, Takashi Aoki, Akira Onozawa (NTT, Japan) |
Page | pp. 503 - 507 |
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Title | Direct Memory Access Transfer Method with Chaining for Inter-Chip Network |
Author | *Eiichi Sasaki, Daisuke Sasaki, Ikan Wang, Yusuke Koizumi, Hideharu Amano (Keio Univ., Japan) |
Page | pp. 508 - 509 |
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Title | Efficient Barrier Synchronization for 2D Meshed NoC-based Many-core Processors |
Author | *Lovic Gauthier, Farhad Mehdipour, Koji Inoue, Shinya Ueno, Hiroshi Sasaki (Kyushu Univ., Japan) |
Page | pp. 510 - 515 |
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Title | Effective Distributed Parallel Scheduling Methodology for Mobile Cloud Computing |
Author | *Hiromasa Yamauchi, Koji Kurihara, Toshiya Otomo (Fujitsu Laboratories Ltd., Japan), Yuta Teranishi (Fujitsu Kyushu Network Technologies Ltd., Japan), Takahisa Suzuki, Koichiro Yamashita (Fujitsu Laboratories Ltd., Japan) |
Page | pp. 516 - 521 |
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Title | Extending Intent in Android for Distributed Collaboration Framework |
Author | *Takahiro Ito, Takuya Azumi, Nobuhiko Nishio (Ritsumeikan Univ., Japan) |
Page | pp. 522 - 527 |
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Title | Energy Efficient Instruction-set Extension Considering Inline Expansion |
Author | *Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan) |
Page | pp. 528 - 533 |
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Title | Reduction of Glitches for Low-Power Multipliers Using 4-2 Compressors Based on Hybrid-CMOS Logic Style |
Author | *Yang-uk Son, Yuzuru Shizuku, Takeshi Kogure, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 534 - 538 |
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Title | Affine Transformations of Logic Functions and Their Application to Affine Decompositions of Index Generation Functions |
Author | *Tsutomu Sasao, Masao Maeta (Kyushu Inst. of Tech., Japan), Radomir Stankovic (Univ. of Nis, Serbia), Stanislav Stankovic (Tampere Univ. of Tech., Finland) |
Page | pp. 539 - 543 |
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Title | An Error Diagnosis Technique Based on SAT Solver |
Author | *Tomoki Matsuyama, Hiroto Senzaki, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 544 - 548 |
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Title | Performance Evaluation of Various Configuration of Adder in Variable Latency Circuits with Error Detection/Correction Mechanism |
Author | *Kenta Ando, Atsushi Takahashi (Osaka Univ., Japan) |
Page | pp. 549 - 554 |
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Title | A Delay Control Technique for Extremely Low-Voltage Subthreshold CMOS Digital Circuits |
Author | *Seiichiro Shiga, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 555 - 559 |
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