SASIMI 2004

Place: Kanazawa Excel Hotel Tokyu, Kanazawa, Japan

Date: October 18 (Mon.) - 19 (Tue.), 2004.

In Cooperation with:

• IEEE Nagoya Section
• The Institute of Electronics, Information and Communication Engineers (IEICE)
• Information Processing Society of Japan (IPSJ)
• Semiconductor Technology Academic Research Center (STARC)

Supported by:

• Ishikawa Prefecture
• Kanazawa City
• The Telecommunications Advancement Foundation (TAF)

Aims of the Workshop

This workshop will provide an interchange forum on system design methodology and CAD/DA technologies for LSI and VLSI. Presentations on theoretical aspects, practical issues, case studies and applications are encouraged. The workshop gives an opportunity for presentation and discussion of advanced work and research. Works in progress and new ideas are also welcome.

Areas of Interest include, but are not limited to:

• Layout/Logic/Behavioral Synthesis
• Test, Verification and Simulation
• System Design and Design Experiences
• Embedded Software Design
• Analog and Mixed-Signal Design
• New Design Methodologies (HW/SW Codesign, MEMS, etc.)

Advance Program and Call for Participation

• Call For Participation (PDF 37KB)
• Final Program (HTML)
• Final Program & Call for Participation (PDF 106KB)
• Call for Papers (for your reference) (PDF 25KB)

Highlight of the Program

• Keynote
  • Prof. Chenming Hu (Univ. of California, Berkeley, USA)
    "Future Directions of Silicon Devices"
• Invited Talks
  • Dr. Sani Nassif (IBM Corp., USA)
    "Model to Hardware Closure for nm Generation Technologies"
  • Prof. Masahiko Yoshimoto (Kobe Univ., Japan)
    "Low Power VLSI Video Compression Processor"
  • Dr. Rudy Lauwereins (IMEC, Belgium)
    "A Vision towards an Ambient Intelligent Environment and the Associated System Level Design Challenges"
  • Prof. H.-S. Philip Wong (Stanford Univ., USA)
    "Nanodevices beyond Silicon: Device and Circuit Implications"
  • Prof. Chein-Wei Jen (ITRI, Taiwan)
    "A DSP Core for Portable Multimedia Application"
  • Prof. Jan Rabaey (Univ. of California, Berkeley, USA)
    "Ultra-Low Power Design: The Road to Disappearing Electronics"
• Panel Discussion

  Title:

  Life at the End of CMOS Scaling

  Organizer and Moderator:

  Prof. Rob Rutenbar (Carnegie Mellon Univ., USA)

  Panelists:

  • Dr. Sani Nassif (IBM Corp., USA)
  • Prof. Jan Rabaey (Univ. of California, Berkeley, USA)
  • Prof. H.-S. Philip Wong (Stanford Univ., USA)
  • Dr. Kazuo Yano (Hitachi Ltd., Japan)

Advance Registration & Hotel Reservation

• Advance Registration: All participants including invited speakers, panelists, moderators, and session chairs are required to make registration. Advance registration deadline is September 17, 2004.
• Hotel Reservation: Application form for hotel reservation should be directly sent to Nippon Travel Agency (NTA) Kanazawa Travel Branch by September 17, 2004.
• For more information, please visit the Advance Registration & Hotel Reservation page.

Conference Venue

• Kanazawa is located on the west coast of Japan's main island, almost in the geographical center of Japan.
• It takes 50 minutes by an airport limousine bus from Komatsu International Airport (KMQ).
• For more information, please visit the Convention Venue and Access Guide page.

Committees of SASIMI 2004

History of SASIMI Workshop

Questions should be directed to:

SASIMI 2004, c/o Prof. Hidetoshi Onodera
Dept. of Communications and Computer Eng., Graduate School of Informatics, Kyoto University
Yoshida-Honmachi, Sakyo-ku, Kyoto 606-8501, JAPAN
Phone: +81-75-753-5314
FAX: +81-75-753-5343
E-mail: sasimi04@arch.ce.hiroshima-cu.ac.jp