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Thursday, March 8, 2012 |
Title | Robust System Design: Overcoming Complexity and Reliability Challenges |
Author | *Subhasish Mitra (Stanford Univ., U.S.A.) |
Page | p. 1 |
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Title | TOF-based 3-Dimensional Head-Tracking System for Repetitive Transcranial Magnetic Stimulation |
Author | *Ryo Ebisuwaki, Yoshihiro Yasumuro, Hiroshige Dan, Masahiko Fuyuki (Kansai Univ., Japan) |
Page | pp. 2 - 5 |
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Title | A High-speed H.264/AVC CABAC Decoder for 4K Video Utilizing Residual Data Accelerator |
Author | *Kenji Watanabe (Synthesis Corp., Japan), Gen Fujita (Osaka Electro-Communication Univ., Japan), Toru Homemoto, Ryoji Hashimoto (Osaka Univ., Japan) |
Page | pp. 6 - 10 |
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Title | Low Power Decision Tree-Based Flow Search Engine |
Author | *Eita Kobayashi, Norio Yamagaki, Takashi Takenaka, Satoshi Kamiya (NEC Corp., Japan), Masato Motomura (Hokkaido Univ., Japan) |
Page | pp. 11 - 16 |
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Title | Manycore NOC Based 2400-PE Network on Chip Emulation and Verification Environment |
Author | *Omar Hammami (ENSTA ParisTech, France), Xinyu Li (EVE, France) |
Page | pp. 17 - 21 |
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Title | Bit-Selective SAD and Its Evaluation |
Author | Ryosuke Hamaji, Yongson Choi, Yuko Hara-Azumi, *Shigeru Yamashita (Ritsumeikan Univ., Japan) |
Page | pp. 22 - 27 |
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Title | A Technique for Accelerating SVM-Based Image Recognition Using GPU |
Author | *Jin Sasaki, Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 28 - 32 |
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Title | Variation of Substrate Sensitivity in Differential Pair Transistors |
Author | *Satoshi Takaya, Takashi Hasegawa, Yoji Bando (Kobe Univ., Japan), Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete, Japan), Makoto Nagata (Kobe Univ., Japan) |
Page | pp. 33 - 35 |
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Title | Automatic Generation of GNU Binutils and GDB for Custom Processors Based on Plug-in Method |
Author | Takahiro Kumura (NEC Corp., Japan), Soichiro Taga (Mitsubishi Electric Micro-Computer Application Software Co., Ltd., Japan), *Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan) |
Page | pp. 36 - 41 |
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Title | Accelerating Regression Test of Compilers by Test Program Merging |
Author | *Takayuki Fukumoto (Kwansei Gakuin Univ., Japan), Kazushi Morimoto (Nomura Research Institute, Ltd., Japan), Nagisa Ishiura (Kwansei Gakuin Univ., Japan) |
Page | pp. 42 - 47 |
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Title | Random Testing of C Compilers Targeting Arithmetic Optimization |
Author | *Eriko Nagai (Kwansei Gakuin Univ., Japan), Hironobu Awazu (Fujitsu, Japan), Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Naoya Takeda (ITEC Hankyu Hanshin, Japan) |
Page | pp. 48 - 53 |
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Title | Compiler-Assisted Soft Error Correction by Duplicating Instructions for VLIW Architecture |
Author | Yunrong Li, Jongwon Lee (Seoul National Univ., Republic of Korea), *Yohan Ko, Kyoungwoo Lee (Yonsei Univ., Republic of Korea), Yunheung Paek (Seoul National Univ., Republic of Korea) |
Page | pp. 54 - 59 |
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Title | Compiler Generation Method from ADL for ASIP Integrated Development Environment |
Author | *Yusuke Hyodo, Kensuke Murata (Osaka Univ., Japan), Takuji Hieda (Ritsumeikan Univ., Japan), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan) |
Page | pp. 60 - 65 |
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Title | Mono-instruction Computer on a Dynamically Reconfigurable Gate Array |
Author | *Yuki Nihira, Minoru Watanabe (Shizuoka Univ., Japan) |
Page | pp. 66 - 70 |
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Title | ASPE: an Abstruction Framework using ALU Arrays for Scalable Multiple FPGAs System |
Author | Kenta Inakagata, *Takayuki Akamine, Hirokazu Morishita (Keio Univ., Japan), Yasunori Osana (Ryukyu Univ., Japan), Naoyuki Fujita (Japan Aerospace Exploration Agency, Japan), Hideharu Amano (Keio Univ., Japan) |
Page | pp. 71 - 76 |
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Title | Robust Register Files by Exploiting Asymmetric Soft Error Rate |
Author | *Yohan Ko, Kyoungwoo Lee (Yonsei Univ., Republic of Korea) |
Page | pp. 77 - 81 |
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Title | Performance Comparison of RG-DTM PUF and Arbiter-based PUFs |
Author | *Kousuke Ogawa, Mitsuru Shiozaki, Kota Furuhashi, Kohei Hozumi, Takeshi Fujino (Ritsumeikan Univ., Japan) |
Page | pp. 82 - 87 |
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Title | Hardware Architecture for Accelerating Monte Carlo based SSTA using Generalized STA Processing Element |
Author | *Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ., Japan) |
Page | pp. 88 - 93 |
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Title | Head-Tail Expressions for Interval Functions |
Author | *Infall Syafalni, Tsutomu Sasao (Kyushu Inst. of Tech., Japan) |
Page | pp. 94 - 99 |
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Title | A Performance Monitoring Tool Suite for Software and SoC On-Chip Bus |
Author | *Yi-Hao Chang, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan) |
Page | pp. 100 - 105 |
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Title | Backward Multiple Time-frame Expansion for Accelerating Sequential SAT |
Author | *Kousuke Torii, Kazuhiro Nakamura (Nagoya Univ., Japan), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan) |
Page | pp. 106 - 110 |
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Title | On Optimization of Power Network Synthesis for Multiple Power Domain Designs |
Author | Chieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, *Hung-Ming Chen (National Chiao Tung Univ., Taiwan) |
Page | pp. 111 - 114 |
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Title | Thermal-Aware Placement for Hotspot Mitigation in 3D FPGAs |
Author | *Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang (National Chiao Tung Univ., Taiwan) |
Page | pp. 115 - 120 |
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Title | Efficient Delay Cells for Wave Pipelined Multifunctional Unit |
Author | Atsushi Kurokawa, *Tatsuya Takaki, Masa-aki Fukase (Hirosaki Univ., Japan) |
Page | pp. 121 - 126 |
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Title | An Integrated Smart Current Sensing Current-Mode Buck Converter |
Author | *Chia-Min Chen, Kai-Hsiu Hsu, Chung-Chih Hung (National Chiao Tung Univ., Taiwan) |
Page | pp. 127 - 130 |
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Title | Linear Time Estimation of Full-Chip Statistical Leakage Current |
Author | *Katsumi Homma (Fujitsu Laboratories Ltd., Japan) |
Page | pp. 131 - 134 |
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Title | An Effective Overlap Removable Objective for Analytical Placement |
Author | *Syota Kuwabara, Yukihide Kohira (Univ. of Aizu, Japan), Yasuhiro Takashima (Univ. of Kitakyushu, Japan) |
Page | pp. 135 - 140 |
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Title | Energy Harvesting for Self Powered Sensor Systems - Case Study: Vibration Energy Harvesting for ‘Intelligent Tire’ Application - |
Author | *Rob van Schaijk, Rene Elfrink, Valer Pop, Ruud Vullers (Imec / Holst Centre, Netherlands) |
Page | pp. 141 - 146 |
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Title | A Formal Full Bus TLM Modeling for Fast and Accurate Contention Analysis |
Author | *Mao-Lin Li, Chen-Kang Lo, Li-Chun Chen (National Tsing Hua Univ., Taiwan), Hong-Jie Huang, Jen-Chieh Yeh (ITRI, Taiwan), Ren-Song Tsay (National Tsing Hua Univ., Taiwan) |
Page | pp. 147 - 152 |
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Title | A Formal Approach to Designing Arithmetic Circuits over Galois Fields Using Symbolic Computer Algebra |
Author | *Kazuya Saito, Naofumi Homma, Takafumi Aoki (Tohoku Univ., Japan) |
Page | pp. 153 - 158 |
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Title | Optimal Design of Allpass Digital Filters using Artificial Bee Colony |
Author | *Wei-Der Chang (Shu-Te Univ., Taiwan), Shing-Tai Pan (National Univ. of Kaohsiung, Taiwan), Kuo-Hua Cheng, Ming-Chieh Hsu (Shu-Te Univ., Taiwan) |
Page | pp. 159 - 162 |
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Title | A Processor Architecture for Multi-Dimensional Parity Check Code Processing |
Author | *Ryota Endo (Osaka Univ., Japan), Hiroki Ohsawa (Fuji Xerox Co., Ltd, Japan), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan) |
Page | pp. 163 - 167 |
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Title | Application on the Hardware/Software Co-simulator; Implementation of Multi-stage, Multi-rate 2-D filter |
Author | *Yukiko Takanishi (Tokyo Metropolitan Univ., Japan), Yuichi Nakamura (NEC Corp., Japan), Takao Nishitani (Tokyo Metropolitan Univ., Japan) |
Page | pp. 168 - 173 |
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Title | Checkpoint Selection for DEPS Framework Based on Quantitative Evaluation of DEPS Profile |
Author | *Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro, Hiroaki Takada (Nagoya Univ., Japan) |
Page | pp. 174 - 179 |
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Title | Model-Based Generation of a Fast and Accurate Virtual Execution Platform for Software-Intensive Real-Time Embedded Systems |
Author | *Jochen Zimmermann, Martin Küster, Oliver Bringmann (FZI Karlsruhe, Germany), Wolfgang Rosenstiel (Univ. Tübingen, Germany) |
Page | pp. 180 - 185 |
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Title | Model Based Parallelization from the Simulink Models and Their Sequential C Code |
Author | *Takahiro Kumura (Osaka Univ./NEC Corp., Japan), Yuichi Nakamura (NEC Corp., Japan), Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan) |
Page | pp. 186 - 191 |
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Title | Saving Power Consumption in Final Stage Adder of Multiplier By Using Difference in Arrival Times with Input Signals |
Author | *Yuzuru Shizuku, Takeshi Kogure, Tatsuya Fujioka, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 192 - 196 |
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Title | A Technique for SAT-based Test Generation through History of Reusing Solutions |
Author | *Kenji Ueda, Fumiyuki Hafuri, Toshiya Mukai, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ., Japan) |
Page | pp. 197 - 198 |
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Title | Reconfigurable Cells for Post-Mask ECO |
Author | *Hiroto Senzaki, Tomoki Matsuyama, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 199 - 204 |
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Title | GPU Acceleration of Cycle-based Soft-Error Simulation for Reconfigurable Array Architectures |
Author | *Takashi Imagawa, Takahiro Oue, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ., Japan) |
Page | pp. 205 - 210 |
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Title | Heterogeneous Assertion-Based Verification for Medical Devices Development |
Author | Stefan Lämmermann (Univ. Tübingen, Germany), Lukas Pielawa (OFFIS, Germany), *Andreas Burger (FZI Karlsruhe, Germany), Jan Schlemminger (OFFIS, Germany), Jürgen Ruf, Thomas Kropf (Univ. Tübingen, Germany), Andreas Hein (OFFIS, Germany), Wolfgang Rosenstiel (Univ. Tübingen, Germany) |
Page | pp. 211 - 216 |
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Title | Degradation of Oscillation Frequency of Ring Oscillators Placed on a 90 nm FPGA |
Author | *Shouhei Ishii, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan) |
Page | pp. 217 - 221 |
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Title | NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs |
Author | Yu-Min Lee, Tsung-Heng Wu (National Chiao Tung Univ., Taiwan), Pei-Yu Huang (ITRI, Taiwan), *Chi-Wen Pan (National Chiao Tung Univ., Taiwan) |
Page | pp. 222 - 226 |
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Title | 2-Stage Simulated Annealing with Crossover Operator for 3D-Packing Volume Minimization |
Author | *Yiqiang Sheng (Tokyo Inst. of Tech., Japan), Atsushi Takahashi (Osaka Univ., Japan), Shuichi Ueno (Tokyo Inst. of Tech., Japan) |
Page | pp. 227 - 232 |
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Title | Thermal Analysis for 3-D ICs Considering Interconnect Power Estimation |
Author | *Chi-Wen Pan, Ying-Hsiang Liu, Yu-Min Lee (National Chiao Tung Univ., Taiwan), Pei-Yu Huang (ITRI, Taiwan), Chi-Ping Yang (National Chiao Tung Univ., Taiwan) |
Page | pp. 233 - 238 |
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Title | Net-based Move in SA-based Placement for a Switch-Block-Free Reconfigurable Device |
Author | *Masato Inagi, Masatoshi Nakamura, Tetsuo Hironaka (Hiroshima City Univ., Japan), Takashi Ishiguro (Taiyo Yuden Co., Ltd., Japan) |
Page | pp. 239 - 240 |
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Title | A Nonlinear Optimization Methodology for Resistor Matching in Analog Integrated Circuits |
Author | *Sheng-Jhih Jiang, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan) |
Page | pp. 241 - 246 |
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Title | Precise Expression of nm CMOS Variability with Variance/Covariance Statistics on Ids(Vgs) |
Author | *Koutaro Hachiya (Jedat, Inc., Japan), Hiroo Masuda (ChiHiro Consultant, Japan), Atsushi Okamoto (Fujitsu Semiconductor Ltd., Japan), Masatoshi Abe, Takeshi Mizoguchi (Toshiba I.S. Corp., Japan), Goichi Yokomizo (STARC, Japan) |
Page | pp. 247 - 252 |
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Title | A Transistor-level Symmetrical Layout Generation for Analog Device |
Author | *Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan) |
Page | pp. 253 - 257 |
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Title | LDPC Coded MIMO Communication System With Relay Selection |
Author | *Nanfan Qiu, Xiao Peng, Yichao Lu, Satoshi Goto (Waseda Univ., Japan) |
Page | pp. 258 - 261 |
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Title | Subkey Driven Power Analysis Attack in Frequency Domain against Cryptographic LSIs |
Author | *Ryusuke Satoh, Daisuke Matsushima, Masaya Yoshikawa (Meijo Univ., Japan) |
Page | pp. 262 - 267 |
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Title | Realtime Mixed Reality Representation with a Virtual Light Source based on a Mobile 3D Acquisition |
Author | *Yoji Watatani, Yoshihiro Yasumuro, Hiroshige Dan, Masahiko Fuyuki (Kansai Univ., Japan) |
Page | pp. 268 - 271 |
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Title | A Full Dynamically Reconfigurable Vision-chip System Including a Lens-array |
Author | *Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito (Shizuoka Univ., Japan) |
Page | pp. 272 - 277 |
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Title | Improved Region-Growing Image-Segmentation Algorithm Using Dynamic Connection Weight Calculation Based on Mean Value of Exited Pixels |
Author | *Naotaka Kawakami, Ryosuke Kimura, Tatsuya Sugahara, Tetsushi Koide, Hans Jürgen Mattausch (Hiroshima Univ., Japan) |
Page | pp. 278 - 283 |
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Title | An Accurate Pedestrian Detection Utilizing Feature of Partitioned Image by Color |
Author | Masashi Ide, *Masataka Takahashi, Yoshiya Sugita, Masahiro Fukui (Ritsumeikan Univ., Japan) |
Page | pp. 284 - 289 |
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Title | A Fast and Accurate Algorithm for Traffic Sign Recognition |
Author | Yoshiya Sugita, *Yuuki Tomisawa, Masashi Ide, Masahiro Fukui (Ritsumeikan Univ., Japan) |
Page | pp. 290 - 295 |
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Title | Challenges for Future System Design and Verification |
Author | Organizer/Moderator: Shinji Kimura (Waseda Univ., Japan), Panelists: Subhasish Mitra (Stanford Univ., U.S.A.), Rob van Schaijk (Imec / Holst Centre, Netherlands), Jason Cong (UCLA, U.S.A.), Sungjoo Yoo (POSTECH, Republic of Korea), Takahide Yoshikawa (Fujitsu Laboratories Ltd., Japan) |
Page | p. 296 |
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Friday, March 9, 2012 |
Title | Parallelization, Customization and Automation |
Author | *Jason Cong (UCLA, U.S.A.) |
Page | pp. 297 - 299 |
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Title | Replacement of Flip-Flops by Latches and Pulsed Latches for Power and Timing Optimization |
Author | Yao-Ting Wu, *Rung-Bin Lin (Yuan Ze Univ., Taiwan) |
Page | pp. 300 - 304 |
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Title | A Routability-oriented Packing Method for FPGA with Fracturable Logic Elements |
Author | Wei Chen (Waseda Univ., Japan), Yuichi Nakamura (NEC Corp., Japan), *Nan Liu, Takeshi Yoshimura (Waseda Univ., Japan) |
Page | pp. 305 - 310 |
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Title | A Two-Step BIST Scheme for Operational Amplifier |
Author | *Jun Yuan, Masayoshi Tachibana (Kochi Univ. of Tech., Japan) |
Page | pp. 311 - 316 |
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Title | Circuit Partitioning Methods for FPGA-based ASIC Emulator using High-speed Serial Wires |
Author | *Katsunori Takahashi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ., Japan) |
Page | pp. 317 - 318 |
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Title | Timing-aware Description Methods and Gate-level Simulation of Single Flux Quantum Logic Circuits |
Author | *Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan) |
Page | pp. 319 - 324 |
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Title | Design and Analysis of Via-Configurable Routing Fabrics for Structured ASICs |
Author | Hsin-Pei Tsai, *Rung-Bin Lin, Liang-Chi Lai (Yuan Ze Univ., Taiwan) |
Page | pp. 325 - 329 |
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Title | Device-level Simulations of Parasitic Bipolar Mechanisim on Preventing MCUs of Redundant Filp-Flops |
Author | *Kuiyuan Zhang, Ryosuke Yamamoto, Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan) |
Page | pp. 330 - 333 |
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Title | A Method of Analog IC Placement with Common Centroid Constraints |
Author | *Keitaro Ue, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan) |
Page | pp. 334 - 339 |
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Title | GPU-based Line Probing Techniques for Mikami Routing Algorithm |
Author | *Chiu-Yi Chan (Yuan Ze Univ., Taiwan), Jiun-Li Lin (National Cheng Kung Univ., Taiwan), Lung-Sheng Chien (National Tsing Hua Univ., Taiwan), Tsung-Yi Ho (National Cheng Kung Univ., Taiwan), Yi-Yu Liu (Yuan Ze Univ., Taiwan) |
Page | pp. 340 - 344 |
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Title | Topology Design for Power Delivery in 3-D Integrated Circuits |
Author | *Shu-Han Wei, Yi-Hsuan Lee, Chih-Ting Sun, Yu-Min Lee (National Chiao Tung Univ., Taiwan), Liang-Chia Cheng (ITRI, Taiwan) |
Page | pp. 345 - 350 |
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Title | A Spur-Reduction Frequency Synthesizer For Wireless Application |
Author | *Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung (National Chiao Tung Univ., Taiwan) |
Page | pp. 351 - 354 |
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Title | Definite Feature of Low-Energy Operation of Scaled Cross-Current Tetrode (XCT) SOI CMOS Circuits |
Author | *Yasuhisa Omura, Daishi Ino (Kansai Univ., Japan) |
Page | pp. 355 - 360 |
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Title | A Matching Method for Look-ahead Assertion on Pattern Independent Regular Expression Matching Engine |
Author | *Yoichi Wakaba, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ., Japan) |
Page | pp. 361 - 366 |
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Title | Highly-parallel AES Processing for Five Confidentiality Modes with Massive-Parallel SIMD Matrix Processor |
Author | *Hiroki Yoshikawa, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ., Japan) |
Page | pp. 367 - 371 |
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Title | A Trace-Back Method with Source States and its Application to Viterbi Decoders of Low Power and Short Latency |
Author | *Kazuhito Ito (Saitama Univ., Japan) |
Page | pp. 372 - 377 |
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Title | Evaluation of Migration Methods for Island Based Parallel Genetic Algorithm on CUDA |
Author | *Yuri Ardila, Shigeru Yamashita (Ritsumeikan Univ., Japan) |
Page | pp. 378 - 383 |
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Title | FPGA Design of User Monitoring System for Display Power Control |
Author | *Tomoaki Ando, Vasily Moshnyaga (Fukuoka Univ., Japan) |
Page | pp. 384 - 389 |
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Title | A Debug Solution with Synchronizer for CDC |
Author | *Akitoshi Matsuda (Kyushu Univ., Japan), Shinichi Baba (Kyushu Embedded Forum, Japan) |
Page | pp. 390 - 393 |
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Title | A Low Power-Delay Product Processor Using Multi-valued Decision Diagram Machine |
Author | *Hiroki Nakahara (Kagoshima Univ., Japan), Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech., Japan) |
Page | pp. 394 - 395 |
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Title | A TMR-based Soft Error Mitigation Technique With Less Area Overhead in High-Level Synthesis |
Author | Daiki Tsuruta, *Masayuki Wakizaka, Yuko Hara-Azumi, Shigeru Yamashita (Ritsumeikan Univ., Japan) |
Page | pp. 396 - 401 |
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Title | Pipeline Circuit Synthesis from C Descriptions for Fast Memory Access in System LSI |
Author | *Yu-ichi Kitamura (Kinki Univ., Japan), Kazuya Kishida (Panasonic Industrial Devices S&T, Japan), Takashi Kambe (Kinki Univ., Japan) |
Page | pp. 402 - 407 |
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Title | A PE-based Pipelining and Assignment Algorithm for Coarse Grained Dynamic Reconfigurable Circuits |
Author | *Nobuyuki Araki, Takashi Kambe (Kinki Univ., Japan) |
Page | pp. 408 - 413 |
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Title | High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement |
Author | *Yuko Hara-Azumi (Univ. of California, Irvine, U.S.A.), Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeikan Univ., Japan), Nikil D. Dutt (Univ. of California, Irvine, U.S.A.) |
Page | pp. 414 - 419 |
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Title | A Method of Power Supply Voltage Assignment and Scheduling of Operations to Reduce Energy Consumption of Error Detectable Computations |
Author | *Yuki Suda, Kazuhito Ito (Saitama Univ., Japan) |
Page | pp. 420 - 424 |
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Title | Software Design Methodology based on Energy Consumption Model Considering Relationship between Software and Hardware |
Author | *Koji Kurihara, Hiromasa Yamauchi, Toshiya Otomo, Takahisa Suzuki (Fujitsu Laboratories Ltd., Japan), Yuta Teranishi (Fujitsu Kyushu Network Technologies Ltd., Japan), Koichiro Yamashita (Fujitsu Laboratories Ltd., Japan) |
Page | pp. 425 - 430 |
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Title | Electro-Thermal Modeling and Reliability Simulation of Power MOSFETs with SystemC-AMS - Case Study: An Unclamped Inductive Switching Test Circuit |
Author | *Keiji Nakabayashi, Takahiro Ozasa (Keirex Technology Inc., Japan), Tamiyo Nakabayashi (Nara Women's Univ., Japan) |
Page | pp. 431 - 436 |
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Title | Innovating the SoC Design for Emerging Memory Technologies |
Author | *Sungjoo Yoo (POSTECH, Republic of Korea) |
Page | pp. 437 - 438 |
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Title | Design Automation for Digital Microfluidic Biochips: From Fluidic-Level Toward Chip-Level |
Author | Tsung-Wei Huang, *Tsung-Yi Ho (National Cheng Kung Univ., Taiwan) |
Page | pp. 439 - 444 |
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Title | Timing-Aware Clock Gating Algorithm for Pulse-Latch Circuits |
Author | *Zong-Han Yang, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan) |
Page | pp. 445 - 450 |
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Title | Resistivity-based Modeling of Substrate Non-uniformity for Resistance Extraction of Low-Resistivity Substrate |
Author | *Yasuhiro Ogasahara, Toshiki Kanamoto (Renesas Electronics Corp., Japan), Hisato Inaba, Toshiharu Chiba (Renesas Design Corp., Japan) |
Page | pp. 451 - 456 |
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Title | Temperature-Constrained Fixed-Outline Floorplanning for 3D ICs |
Author | Ciao-Yu Hong, Wai-Kei Mak, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan) |
Page | pp. 457 - 459 |
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Title | A GPGPU Implementation of Parallel Backward Euler Algorithm for Power Grid Circuit Simulation |
Author | Lei Lin, *Hayato Shiono, Makoto Yokota, Masahiro Fukui (Ritsumeikan Univ., Japan) |
Page | pp. 460 - 465 |
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Title | A Third Order Delta-Sigma Modulator with Shared Opamp Technique for Wireless Applications |
Author | *Ghazal Fahmy, Daisuke Kanemoto, Haruichi Kanaya, Ramesh Pokharel, Keiji Yoshida (Kyushu Univ., Japan) |
Page | pp. 466 - 467 |
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Title | A Self-Organization Maps Approach to FPGA Placement |
Author | Motoki Amagasaki, *Yasuaki Tomonari, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ., Japan) |
Page | pp. 468 - 469 |
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Title | The Development of CAD System for Via Programmable Structured ASIC VPEX3 |
Author | *Ryohei Hori (Ritsumeikan Univ., Japan), Masaya Yoshikawa (Meijo Univ., Japan), Takeshi Fujino (Ritsumeikan Univ., Japan) |
Page | pp. 470 - 475 |
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Title | Design of Low-Voltage High-Precision Complex Quadrature Modulators |
Author | *Takahiro Tsushima, Tsuneo Tsukahara (Univ. of Aizu, Japan) |
Page | pp. 476 - 481 |
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Title | A Design of 2GHz Band O-QPSK Wireless Transmitter using 0.18µmCMOS Technology |
Author | *Yuki Mitani, Nobuhiko Nakano (Keio Univ., Japan) |
Page | pp. 482 - 483 |
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Title | A 0.5V PWM-Driven Analog Differential Amplifier Using Subthreshold Leakage Current |
Author | *Tomochika Harada, Ryuuya Otaki (Yamagata Univ., Japan) |
Page | pp. 484 - 487 |
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Title | 16PE 3D-Mesh NOC Based 3D Multicore Design and Implementation |
Author | Mohamad Hairol Jabbar (ENSTA ParisTech, France), Dominique Houzet (GIPSA-LAB, France), *Omar Hammami (ENSTA ParisTech, France) |
Page | pp. 488 - 489 |
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Title | A Performance Improvement for Floating-Point Arithmetic Unit with Precision Degradation Detection |
Author | *Soseki Aniya, Toshiaki Kitamura (Hiroshima City Univ., Japan) |
Page | pp. 490 - 491 |
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Title | Hardware Architecture for Real-Time Operation of Learning-Based Super-Resolution Using Binary Search Tree |
Author | *Takahiro Kitayama, Kohei Michibata, Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 492 - 496 |
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Title | Architecture Optimization of Group Signature Circuits for Cloud Computing Environment |
Author | *Sumio Morioka, Jun Furukawa, Yuichi Nakamura, Kazue Sako (NEC Corp., Japan) |
Page | pp. 497 - 502 |
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Title | Efficient Packet Transmission Priority Control Method for Network-on-Chip |
Author | *Yusuke Sekihara, Takashi Aoki, Akira Onozawa (NTT, Japan) |
Page | pp. 503 - 507 |
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Title | Direct Memory Access Transfer Method with Chaining for Inter-Chip Network |
Author | *Eiichi Sasaki, Daisuke Sasaki, Ikan Wang, Yusuke Koizumi, Hideharu Amano (Keio Univ., Japan) |
Page | pp. 508 - 509 |
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Title | Efficient Barrier Synchronization for 2D Meshed NoC-based Many-core Processors |
Author | *Lovic Gauthier, Farhad Mehdipour, Koji Inoue, Shinya Ueno, Hiroshi Sasaki (Kyushu Univ., Japan) |
Page | pp. 510 - 515 |
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Title | Effective Distributed Parallel Scheduling Methodology for Mobile Cloud Computing |
Author | *Hiromasa Yamauchi, Koji Kurihara, Toshiya Otomo (Fujitsu Laboratories Ltd., Japan), Yuta Teranishi (Fujitsu Kyushu Network Technologies Ltd., Japan), Takahisa Suzuki, Koichiro Yamashita (Fujitsu Laboratories Ltd., Japan) |
Page | pp. 516 - 521 |
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Title | Extending Intent in Android for Distributed Collaboration Framework |
Author | *Takahiro Ito, Takuya Azumi, Nobuhiko Nishio (Ritsumeikan Univ., Japan) |
Page | pp. 522 - 527 |
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Title | Energy Efficient Instruction-set Extension Considering Inline Expansion |
Author | *Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ., Japan) |
Page | pp. 528 - 533 |
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Title | Reduction of Glitches for Low-Power Multipliers Using 4-2 Compressors Based on Hybrid-CMOS Logic Style |
Author | *Yang-uk Son, Yuzuru Shizuku, Takeshi Kogure, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 534 - 538 |
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Title | Affine Transformations of Logic Functions and Their Application to Affine Decompositions of Index Generation Functions |
Author | *Tsutomu Sasao, Masao Maeta (Kyushu Inst. of Tech., Japan), Radomir Stankovic (Univ. of Nis, Serbia), Stanislav Stankovic (Tampere Univ. of Tech., Finland) |
Page | pp. 539 - 543 |
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Title | An Error Diagnosis Technique Based on SAT Solver |
Author | *Tomoki Matsuyama, Hiroto Senzaki, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 544 - 548 |
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Title | Performance Evaluation of Various Configuration of Adder in Variable Latency Circuits with Error Detection/Correction Mechanism |
Author | *Kenta Ando, Atsushi Takahashi (Osaka Univ., Japan) |
Page | pp. 549 - 554 |
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Title | A Delay Control Technique for Extremely Low-Voltage Subthreshold CMOS Digital Circuits |
Author | *Seiichiro Shiga, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 555 - 559 |
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Title | K Computer: Challenges making the Superior Quality Interconnect |
Author | *Takahide Yoshikawa (Fujitsu Laboratories Ltd., Japan) |
Page | pp. 560 - 564 |
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